Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors
Job Summary
Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors.
This is a rare opportunity to shape the CPU architecture at the heart of our AI platform and lead one of the most strategic technical efforts at Tenstorrent.
We welcome candidates at various experience levels and will assess for the appropriate level during the interview process.
Matching Summary
Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors.
Skills & Requirements
Must-have
RISC-V CPU architecture
CPU performance modeling
microarchitecture design
C++ and Python proficiency
RISC-V instruction-set
compiler design impact
AI workload analysis
Nice-to-have
collaboration and curiosity
solving hard problems
developer experience focus
open-source RISC-V cores
LLVM toolchains
Key Requirements
10+ years in CPU performance modeling and microarchitecture
Proficient in C++ and Python
Strong understanding of RISC-V instruction-set
Well versed in compiler design
Familiar with open-source RISC-V cores and LLVM toolchains
Eligibility to access U.S. export-controlled technology
Work Rights
Eligibility to access U.S. export-controlled technology