Application Engineer

Cadence

San Jose, US
Base: $74,200 to $137,800; bonus/equity: incentive...
On-site
Rtl design with system verilog
Formal property-checking tools
Unix and scripting languages
Collaborate with prominent semiconductor and system companies to implement Cadence’s Jasper Formal Verification, Chipstack and AI solutions

Job Summary

  • Collaborate with prominent semiconductor and system companies to implement Cadence’s Jasper Formal Verification, Chipstack and AI solutions.
  • Provide hands-on technical support throughout both the pre-sale and post-sale stages, addressing and resolving complex verification challenges for customers.
  • Partner with R&D teams to introduce innovative formal flows and applications to customers, advocate for their needs, and assist in the development of competitive and inventive solutions.

Matching Summary

Collaborate with prominent semiconductor and system companies to implement Cadence’s Jasper Formal Verification, Chipstack and AI solutions.

Salary

Base: $74,200 to $137,800; Bonus/Equity: Incentive compensation structure; Benefits: Paid vacation, 401(k), ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • RTL design with System Verilog
  • Formal property-checking tools
  • UNIX and scripting languages
  • EDA tool administration
  • Customer-facing technical support

Nice-to-have

  • Mentoring junior team members
  • Representing Cadence at conferences
  • Understanding competitive landscape

Key Requirements

  • At least seven years of relevant industry experience
  • Advanced degree in a related field highly desirable
  • Proficiency in TCL scripting
  • Familiarity with simulation-based verification concepts

Work Rights

Not specified

Tailored Resume

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