Senior Design Technology Co-optimization Engineer

Google

Sunnyvale, CA, United States
Base: $163,000-$237,000; bonus/equity: included; b...
Not specified
Place and route experiments
Ppa sensitivity analysis
Standard cell library architecture
Google is seeking a Senior Design Technology Co-optimization Engineer to advance TPU technology for AI/ML hardware acceleration. The role involves collaborating across teams to optimize silicon design while focusing on improving power efficiency and performance metrics

Job Summary

  • This role drives the future of AI/ML hardware acceleration by defining next-generation data center-class silicon.
  • You will conduct high-fidelity Place and Route experiments to evaluate the impact of advanced process features on performance and power.
  • The position offers a competitive base salary ranging from $163,000 to $237,000 plus bonus, equity, and benefits.

Matching Summary

Match Score: 85

Google is seeking a Senior Design Technology Co-optimization Engineer to advance TPU technology for AI/ML hardware acceleration. The role involves collaborating across teams to optimize silicon design while focusing on improving power efficiency and performance metrics.

Salary

Base: $163,000-$237,000; Bonus/Equity: Included; Benefits: Not specified

Skills & Requirements

Must-have

  • Place and Route experiments
  • PPA sensitivity analysis
  • Standard cell library architecture
  • Metal stack definitions
  • Foundry collaboration
  • Automated physical design methodologies

Nice-to-have

  • System Technology Co-Optimization experience
  • Emerging transistor architectures knowledge
  • Backside power delivery expertise
  • Power density optimization skills

Key Requirements

  • Experience with advanced logic nodes
  • Expertise in digital design verification
  • Background in TPU architecture integration

Work Rights

Not specified

Tailored Resume

Cover Letter