Senior Design Verification Engineer

Inteelabs

Santa Clara, California, US
$190,610.00-269,100.00 usd; not specified; not spe...
End-to-end verification
Testbench architecture
Protocol verification
Own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff

Job Summary

  • Own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff.
  • Build scalable verification environments and targeted testplans with reusable testbenches, checkers, VIPs, and behavioral models.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

Own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff.

Salary

$190,610.00-269,100.00 USD; Not specified; Not specified

Skills & Requirements

Must-have

  • end-to-end verification
  • testbench architecture
  • protocol verification
  • memory subsystem behavior
  • AI-assisted workflows
  • simulation and formal verification

Nice-to-have

  • adaptability and attention to detail
  • collaboration with cross-functional teams
  • mentoring and developing engineers
  • emerging methodologies

Key Requirements

  • 9+ years relevant experience (Bachelor's)
  • 6+ years relevant experience (Master's)
  • IP DV, subsystem and SoC-level verification
  • interconnects, caches, memory subsystems
  • AMBA, PCIe, UCIe, CXL protocols
  • UVM, SVA, ABV, co-simulation
  • SystemVerilog/UVM, C/C++, Python proficiency
  • RTL, physical design, CAD tool flows familiarity

Work Rights

Not specified

Tailored Resume

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