Design Engineering Architect — Memory Modeling Portfolio

Cadence

Seoul, South Korea
Hybrid
Ufs/unipro/mphy/rmmi protocol stack expertise
Systemverilog/verilog rtl design and verification
Hardware emulation debugging skills
This role serves as the primary Korea-based expert for the UFS/Unipro/MPHY/RMMI protocol stack, bridging deep technical knowledge with direct customer partnership

Job Summary

  • This role serves as the primary Korea-based expert for the UFS/Unipro/MPHY/RMMI protocol stack, bridging deep technical knowledge with direct customer partnership.
  • The successful candidate will debug complex memory protocol IP on industry-leading Palladium and Protium hardware emulation platforms while mentoring less experienced engineers.
  • The position requires a senior technical anchor who can translate customer challenges into actionable problem definitions and drive resolution across global R&D teams.

Matching Summary

This role serves as the primary Korea-based expert for the UFS/Unipro/MPHY/RMMI protocol stack, bridging deep technical knowledge with direct customer partnership.

Skills & Requirements

Must-have

  • UFS/Unipro/MPHY/RMMI protocol stack expertise
  • SystemVerilog/Verilog RTL design and verification
  • Hardware emulation debugging skills
  • Customer site presence and consulting
  • Senior technical mentorship capabilities

Nice-to-have

  • Cadence Palladium or Protium platform experience
  • Scripting environments like Perl, TCL, C-shell
  • Cross-cultural customer relationship building
  • Broad protocol exposure beyond UFS stack
  • Collaborative team spirit and emotional intelligence

Key Requirements

  • Master's degree in Electrical Engineering or equivalent
  • 10+ years of relevant industry experience
  • PhD with 8+ years of experience
  • Fluent English written and verbal communication

Work Rights

Not specified

Tailored Resume

Cover Letter