This role offers a unique opportunity to lead timing and convergence efforts for System on Chip (SOC) designs while driving necessary design changes
Job Summary
This role offers a unique opportunity to lead timing and convergence efforts for System on Chip (SOC) designs while driving necessary design changes.
The successful candidate will own the end-to-end timing closure process, including signoff criteria, clocking strategies, and constraint validation across multiple domains.
Candidates must possess deep expertise in advanced timing analysis, ECO creation, and debugging across technology nodes ranging from 28nm down to 7nm.
Matching Summary
This role offers a unique opportunity to lead timing and convergence efforts for System on Chip (SOC) designs while driving necessary design changes.
Salary
Not specified; Not specified; Not specified
Skills & Requirements
Must-have
STA Leader with SOC timing closure experience
Expertise in 28nm 16nm 10nm 7nm technology nodes
Hands-on EDA tools RC DC PT PTSI knowledge
Advanced digital design architecture understanding
Clocking structures and constraint development skills
Nice-to-have
Experience with signal integrity and EM/IR analysis
Scripting contribution for flow methodology
Collaboration with IP functional integration teams
Debugging timing failures and SDF GLS support
Key Requirements
Experience with 28nm 16nm 10nm 7nm nodes
Proficiency in Synthesis Floor planning Place & Route