This role serves as a key technical leader responsible for driving advanced physical design activities for complex SoC and IP blocks
Job Summary
This role serves as a key technical leader responsible for driving advanced physical design activities for complex SoC and IP blocks.
The engineer will optimize design methodologies and flows to achieve challenging performance, power, and area targets for cutting-edge semiconductor products.
Candidates are expected to mentor junior and mid-level engineers while evaluating and integrating new EDA tools to enhance capabilities.
Matching Summary
This role serves as a key technical leader responsible for driving advanced physical design activities for complex SoC and IP blocks.
Skills & Requirements
Must-have
15+ years ASIC physical design experience
RTL to GDSII flow execution
Advanced process node tape-outs
Cadence Innovus or Synopsys Fusion Compiler
Tcl Perl Python scripting proficiency
Nice-to-have
Mentoring junior engineering staff
DFM principles application
New EDA tool integration
Cross-functional collaboration skills
Key Requirements
Bachelor's or Master's degree in Electrical Engineering
15+ years of extensive ASIC physical design experience