Job Summary

• Develop image processing pipeline on Field-Programmable Gate Array (FPGA) using High Level Synthesis (HLS).
• Design FPGA logic using VHDL and Verilog, writing testbenches for functional simulation.
• Create host computer test tools or scripts using C/C++ or Python to test embedded systems.

Matching Summary

Salary

Base: $115,500.00 - $192,500.00; Bonus/Equity: Not specified; Benefits: health, life, retirement, paid time off, and much more

Skills & Requirements

Key Requirements

• Bachelor’s Degree or Equivalent years of directly related experience
• 5 Years of Relevant Experience
• Prior FPGA design experience with HLS
• Proficient with VHDL, Verilog/System Verilog; C/C++; Python
• Proficient with FPGA development environments
• Hands-on experience using standard electronic test equipment

Work Rights