Gpu Design Verification Engineer

Intel

Folsom, California, United States
Base: $105,650.00-149,150.00 usd; bonus/equity: st...
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Bachelor's degree in electrical engineering
Experience with systemverilog and uvm
Experience with computer architecture
** Intel is seeking a GPU Design Verification Engineer to perform functional verification of graphics logic components, ensuring designs meet specification requirements. The role involves developing scalable verification plans, executing simulations, and collaborating with various teams to enhance verification processes. **

Job Summary

  • The role involves defining scalable IP verification plans and test benches to ensure coverage for graphics microarchitecture specifications.
  • Candidates will collaborate with GPU architects and RTL developers to resolve failing tests and improve verification infrastructure.
  • Intel offers a competitive compensation package including stock bonuses, health benefits, and retirement programs.

Matching Summary

Match Score: 75

** Intel is seeking a GPU Design Verification Engineer to perform functional verification of graphics logic components, ensuring designs meet specification requirements. The role involves developing scalable verification plans, executing simulations, and collaborating with various teams to enhance verification processes. **

Salary

Base: $105,650.00-149,150.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, vacation

Skills & Requirements

Must-have

  • Bachelor's Degree in Electrical Engineering
  • Experience with SystemVerilog and UVM
  • Experience with computer architecture
  • ASIC Design and Verification experience
  • Debug experience with simulation models

Nice-to-have

  • GPU architecture knowledge
  • Familiarity with AI tools for design
  • Memory architecture knowledge
  • Test plan coding and execution experience
  • Familiarity with ML tools

Key Requirements

  • 1+ years relevant experience or MS degree
  • SystemVerilog and UVM environment proficiency
  • Computer architecture background required
  • ASIC verification debug skills needed

Work Rights

Not specified

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