Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation, distribution, gating, and domain crossing strategies
Job Summary
Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation, distribution, gating, and domain crossing strategies.
Own the technical roadmap and methodology improvements for clocking, timing closure, and custom circuits, mentoring junior and senior designers.
Partner with foundries, EDA vendors, and internal silicon validation teams to ensure robust silicon correlation and yield.
Matching Summary
Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation, distribution, gating, and domain crossing strategies.
Skills & Requirements
Must-have
SoC clocking networks
clock generation (PLLs, DLLs)
distribution, gating, domain crossing
power-performance-area (PPA) optimization
transistor-level design
spice simulations
post-layout validation
Nice-to-have
high-speed interface IPs
power management circuits
custom memory design
Silicon bring-up, characterization, debug
patents or publications
Key Requirements
15–20 years of hands-on experience
M.Tech / B.Tech / Ph.D. in Electrical/Electronics Engineering