Analog/mixed-signal Ic Design Engineer - Acacia (hybrid)

Cisco UK

San Jose, CA, USA
Base: $168,800 - $241,200; bonus/equity: eligible ...
Hybrid
High speed serial links design
High performance output drivers
Phase locked loops (pll)
This role involves architecting and designing ultra-deep sub-micron CMOS products for 100G to 1.6T+ bit speed fiber optic transmission markets

Job Summary

  • This role involves architecting and designing ultra-deep sub-micron CMOS products for 100G to 1.6T+ bit speed fiber optic transmission markets.
  • The successful candidate will lead efforts for a large block on a complex chip while mentoring team members and participating in peer reviews.
  • Cisco offers competitive compensation ranging from $168,800 to $241,200 plus equity, bonuses, and comprehensive benefits including paid time off and wellness days.

Matching Summary

This role involves architecting and designing ultra-deep sub-micron CMOS products for 100G to 1.6T+ bit speed fiber optic transmission markets.

Salary

Base: $168,800 - $241,200; Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k), paid leave, and volunteer days

Skills & Requirements

Must-have

  • High speed serial links design
  • High performance output drivers
  • Phase locked loops (PLL)
  • Opamps and programmable gain amplifiers
  • Equalization techniques
  • Cadence Virtuoso simulation
  • CMOS process technology

Nice-to-have

  • FinFET and GAA technologies experience
  • High-frequency layout floorplanning
  • Design for manufacturability expertise
  • Laboratory validation and ESD practices
  • Collaborative team-oriented approach
  • Mentoring junior engineers

Key Requirements

  • Bachelor's degree + 8 years experience or Master's + 6 years or PhD + 3 years
  • Experience with 3+ areas of high-speed IC design
  • Proficiency in Cadence tools (Virtuoso, Spectre, Calibre)

Work Rights

Not specified

Tailored Resume

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