The role involves defining configuration requirements for the Peregrine RISC-V subsystem across three critical GPU IPs: PMU, GSP, and SEC
Job Summary
The role involves defining configuration requirements for the Peregrine RISC-V subsystem across three critical GPU IPs: PMU, GSP, and SEC.
Engineers will develop wrapper logic to bridge the Peregrine subsystem with engine interfaces and drive SoC integration efforts through synthesis handoff.
Collaboration with physical design and software teams is essential to optimize partitioning, floorplanning, and system-level performance metrics like memory latency.
Matching Summary
The role involves defining configuration requirements for the Peregrine RISC-V subsystem across three critical GPU IPs: PMU, GSP, and SEC.
Skills & Requirements
Must-have
BS or MS in Electrical Engineering
3+ years relevant work experience
Front-end ASIC design RTL coding
Synthesis lint and CDC verification
SoC integration drive from RTL to synthesis
Nice-to-have
Strong communication across teams
Self-motivated analytical problem solving
Experience with multi-die chiplet architectures
Key Requirements
BS or MS in Electrical Engineering or Computer Engineering