Digital Senior Serdes Design Engineer

Ciena Corporation

Base: $109,000 - $174,000 cad; bonus/equity: discr...
Not specified (assumed flexible due to the company culture).
System verilog proficiency above intermediate level
Digital design synthesis and sta experience
Timing closure and asynchronous clock crossing
Ciena Corporation is seeking a Senior Digital Serdes Design Engineer to design functional blocks for its Wavelogic family of products, which are crucial to its telecommunications solutions. The ideal candidate should possess a strong technical background in digital design and System Verilog, along with excellent problem-solving and communication skills

Job Summary

  • The role involves designing power and area optimized functional blocks for the Wavelogic family of optical fiber transmission products.
  • Candidates are expected to collaborate with systems engineers, architects, and verification teams to produce implementation specifications and debug code.
  • Ciena offers a comprehensive benefits package including medical, dental, vision plans, retirement matching, and paid time off.

Matching Summary

Match Score: 85

Ciena Corporation is seeking a Senior Digital Serdes Design Engineer to design functional blocks for its Wavelogic family of products, which are crucial to its telecommunications solutions. The ideal candidate should possess a strong technical background in digital design and System Verilog, along with excellent problem-solving and communication skills.

Salary

Base: $109,000 - $174,000 CAD; Bonus/Equity: Discretionary incentive bonus eligible; Benefits: Medical, dental, vision, 401(K)/DCPP matching, ESPP

Skills & Requirements

Must-have

  • System Verilog proficiency above intermediate level
  • Digital design synthesis and STA experience
  • Timing closure and asynchronous clock crossing
  • RTL and C source code creation and integration
  • Debugging during simulation and regression verification

Nice-to-have

  • Self-starter with strong independent work ability
  • Excellent written and oral communication skills
  • Experience with digital silicon design backend process
  • Familiarity with Python, Make, bash, or C++
  • Knowledge of IEEE, Ethernet, or OIF standards

Key Requirements

  • BEng/BSc or MEng/MSc in Electrical or Computer Engineering
  • Proficiency with System Verilog for design
  • Experience with formal verification methods

Work Rights

Not specified

Tailored Resume

Cover Letter