Soc/ip Design Verification Engineer

Intel Corporation

Bangalore, India
Hybrid
Uvm testbench development
Constrained-random test content
Coverage closure
You will own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, from requirements decomposition to signoff

Job Summary

  • You will own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, from requirements decomposition to signoff.
  • You will architect and implement UVM environments, develop test content, and debug failures across simulation and emulation.
  • You will collaborate cross-functionally with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.

Matching Summary

You will own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, from requirements decomposition to signoff.

Skills & Requirements

Must-have

  • UVM testbench development
  • constrained-random test content
  • coverage closure
  • debug across levels
  • SystemVerilog development expertise
  • coverage-driven verification workflows

Nice-to-have

  • cross-functional collaboration
  • continuous improvement of flows
  • leading small teams
  • mentoring experience

Key Requirements

  • 5+ years SoC/IP design verification experience
  • BS/MS in Electrical/Computer Engineering or related field
  • Scripting proficiency (Python, Perl, Shell, Make/CMake)

Work Rights

Not specified

Tailored Resume

Cover Letter