Analog Layout Engineer

MARVELL ASIA PTE LTD

Singapore
Not specified
Cadence virtuoso simulation
Analog circuit design
Design verification
Marvell Asia Pte Ltd is seeking an Analog Layout Engineer to work collaboratively with global teams in simulating and verifying designs using Cadence Virtuoso. The ideal candidate will lead design refinements and contribute to the development of advanced semiconductor technologies while mentoring team members

Job Summary

  • The role involves collaborating with global teams to run simulations and verifications using Cadence Virtuoso to drive iterative design refinement.
  • Candidates will contribute as technical mentors throughout the project lifecycle while supporting the development of advanced semiconductor technologies.
  • Responsibilities include overseeing end-to-end development stages from cell design to functional blocks and full chip interfaces across multiple process nodes.

Matching Summary

Match Score: 85

Marvell Asia Pte Ltd is seeking an Analog Layout Engineer to work collaboratively with global teams in simulating and verifying designs using Cadence Virtuoso. The ideal candidate will lead design refinements and contribute to the development of advanced semiconductor technologies while mentoring team members.

Skills & Requirements

Must-have

  • Cadence Virtuoso simulation
  • Analog circuit design
  • Design verification
  • Debugging designs
  • Microelectronic implementation

Nice-to-have

  • Technical mentoring skills
  • Global team collaboration
  • Project lifecycle management
  • High-speed circuit expertise

Key Requirements

  • Expertise in CAD tools
  • Experience with microelectronic layers
  • Ability to manage shifting priorities

Work Rights

Not specified

Tailored Resume

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