Asic Formal Verification Engineer, Tpu Compute

Google

Sunnyvale, CA, United States
Base: $163,000-$237,000; bonus/equity: included; b...
Hybrid
Formal verification sign-off approach
Systemverilog assertions (sva) suites
Reusable formal testbenches development
Google is seeking an ASIC Formal Verification Engineer to work on cutting-edge TPU technology that accelerates AI/ML applications. The role focuses on formal verification of complex digital designs, contributing to the architecture and development of custom silicon solutions for data centers

Job Summary

  • This role involves shaping the future of AI/ML hardware acceleration by driving cutting-edge TPU technology.
  • You will architect, develop, and deploy reusable formal testbenches and high-coverage SystemVerilog Assertions suites across multiple designs.
  • The position offers a competitive US base salary range of $163,000-$237,000 plus bonus, equity, and benefits.

Matching Summary

Match Score: 85

Google is seeking an ASIC Formal Verification Engineer to work on cutting-edge TPU technology that accelerates AI/ML applications. The role focuses on formal verification of complex digital designs, contributing to the architecture and development of custom silicon solutions for data centers.

Salary

Base: $163,000-$237,000; Bonus/Equity: Included; Benefits: Not specified

Skills & Requirements

Must-have

  • Formal verification sign-off approach
  • SystemVerilog Assertions (SVA) suites
  • Reusable formal testbenches development
  • Complex digital design verification
  • TPU architecture integration knowledge

Nice-to-have

  • Silicon bringup experience
  • Continuous integration flow maintenance
  • Dashboarding for verification metrics
  • Collaboration with architecture teams
  • Custom silicon solution innovation

Key Requirements

  • Experience with complex digital designs
  • Expertise in formal verification methodologies
  • Knowledge of TPU architecture

Work Rights

Not specified

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