Digital Senior Verification Engineer

Ciena

Atlanta, GA, US
Base: $119,900 - $191,500 usd; bonus/equity: discr...
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System verilog uvm proficiency
Functional coverage and verification strategies
Simulation and debugging of digital designs
** Ciena is seeking a Digital Senior Verification Engineer to join their team in Atlanta, GA, focusing on the verification of their Wavelogic family of products. The ideal candidate should have strong technical skills in digital verification processes, particularly with System Verilog, UVM, and related tools, while thriving in a collaborative and flexible work environment. **

Job Summary

  • Ciena is a global leader in high-speed connectivity committed to a people-first approach and fostering a flexible work environment that supports individual growth and well-being.
  • The Digital Senior Verification Engineer will propose and implement innovative verification strategies to validate functional blocks of the Wavelogic family of products, contributing to verification planning and test environment creation.
  • Ciena offers competitive compensation with a salary range of $119,900 - $191,500 USD, a comprehensive benefits package, and is an Equal Opportunity Employer valuing diversity and inclusion.

Matching Summary

Match Score: 75

** Ciena is seeking a Digital Senior Verification Engineer to join their team in Atlanta, GA, focusing on the verification of their Wavelogic family of products. The ideal candidate should have strong technical skills in digital verification processes, particularly with System Verilog, UVM, and related tools, while thriving in a collaborative and flexible work environment. **

Salary

Base: $119,900 - $191,500 USD; Bonus/Equity: discretionary incentive bonus for non-sales employees; Benefits: medical, dental, vision, 401(K)/DCPP matching, ESPP, EAP, paid leave

Skills & Requirements

Must-have

  • System Verilog UVM proficiency
  • Functional coverage and verification strategies
  • Simulation and debugging of digital designs
  • Collaboration with systems engineers and architects
  • Coverage-driven verification and regression monitoring

Nice-to-have

  • Experience with formal verification methods
  • Knowledge of OTN/FlexO/B100G and Ethernet protocols
  • Familiarity with GIT and Jira tools
  • Programming skills in Python, Make, bash, C, C++, System C
  • Highly motivated self-starter and team player

Key Requirements

  • Completed degree in electrical/computer engineering or computer science
  • Proficiency above intermediate level with System Verilog, UVM, SVA
  • Experience with major vendor simulators
  • Excellent English communication skills

Work Rights

Not specified

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