Senior Verification Engineer

Altera Corporation

Jerusalem, Israel
Systemverilog/uvm experience
Python scripting for automation
Digital design and computer architecture
Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP

Job Summary

  • Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP.
  • Develop and maintain advanced SystemVerilog/UVM verification environments.
  • Leverage AI-assisted tools as a core part of your daily engineering workflow.

Matching Summary

Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP.

Skills & Requirements

Must-have

  • SystemVerilog/UVM experience
  • Python scripting for automation
  • Digital design and computer architecture
  • Constrained-random verification
  • Coverage-driven verification
  • Mixed-signal IP verification

Nice-to-have

  • Formal verification tools
  • High-speed protocol knowledge
  • DSP algorithm verification
  • AI-assisted engineering tools

Key Requirements

  • 4–7 years of hands-on experience
  • Bachelor's or Master's degree
  • Electrical Engineering, Computer Engineering, or Computer Science

Work Rights

Not specified

Tailored Resume

Cover Letter