The role involves developing SerDes/Transceiver designs across the full FPGA/ASIC digital design flow from specification to hardware validation
Job Summary
The role involves developing SerDes/Transceiver designs across the full FPGA/ASIC digital design flow from specification to hardware validation.
Candidates must demonstrate strong problem-solving skills and the ability to collaborate effectively with cross-functional teams including architects and project managers.
The position requires hands-on experience in functional verification, lint/CDC checks, logic synthesis, and timing analysis for complex digital blocks.
Matching Summary
Match Score: 85
The role involves developing SerDes/Transceiver designs across the full FPGA/ASIC digital design flow from specification to hardware validation.
Skills & Requirements
Must-have
RTL development with Verilog/SystemVerilog
Front-end digital design flow experience
ASIC or FPGA tapeout involvement
Nice-to-have
DFT concepts and hands-on experience
SystemVerilog and UVM knowledge
High-performance digital design background
Key Requirements
Bachelor or Masters Degree in Electronic Engineering