Fpga Digital Design & Verification - Intern

Altera

San Jose, California, United States
Base: $95k - $100k usd; bonus/equity: incentive op...
Systemverilog proficiency
Uvm-based verification experience
Digital logic design foundation
This internship offers hands-on experience developing SystemVerilog/UVM-based verification environments for next-generation FPGA products

Job Summary

  • This internship offers hands-on experience developing SystemVerilog/UVM-based verification environments for next-generation FPGA products.
  • Candidates will collaborate with experienced engineers to debug RTL failures and validate communication protocols like UART and SPI.
  • The role supports critical systems including AI/ML accelerators and memory interfaces within industry-leading SoC platforms.

Matching Summary

This internship offers hands-on experience developing SystemVerilog/UVM-based verification environments for next-generation FPGA products.

Salary

Base: $95K - $100K USD; Bonus/Equity: Incentive opportunities available; Benefits: Not specified

Skills & Requirements

Must-have

  • SystemVerilog proficiency
  • UVM-based verification experience
  • Digital Logic Design foundation
  • Simulation tool usage (VCS, QuestaSim)
  • Computer or Electrical Engineering graduate degree

Nice-to-have

  • Python, Perl, Tcl, or C scripting
  • AXI protocol verification knowledge
  • Intel Quartus Prime or Xilinx Vivado exposure
  • AI/ML accelerator system experience
  • Formal verification concepts familiarity

Key Requirements

  • Currently pursuing Graduate Degree in Computer or Electrical Engineering
  • Eligible for U.S. export authorizations

Work Rights

Must be eligible for U.S. export authorizations

Tailored Resume

Cover Letter