Asic Design Technical Leader – Design & Timing Constraints Focus

Cisco

San Jose, California, US
Base: $168,800.00 to $241,200.00; bonus/equity: no...
Onsite
Sdc development experience
Static timing analysis
Verilog/system verilog programming
Join the Cisco Silicon One team in developing a unified silicon architecture

Job Summary

  • Join the Cisco Silicon One team in developing a unified silicon architecture.
  • You will collaborate with Front-end and Back-end teams to refine design and timing constraints.
  • At Cisco, we innovate fearlessly to create solutions that connect and protect organizations.

Matching Summary

Join the Cisco Silicon One team in developing a unified silicon architecture.

Salary

Base: $168,800.00 to $241,200.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision insurance

Skills & Requirements

Must-have

  • SDC development experience
  • Static Timing Analysis
  • Verilog/System Verilog programming

Nice-to-have

  • Experience with constraint analyzer tools
  • Scripting languages like Python
  • Formal Verification experience

Key Requirements

  • Bachelor’s or Master’s Degree in Engineering
  • 8+ years of ASIC experience
  • Experience with STA tools like PrimeTime/Tempus

Work Rights

Not specified

Tailored Resume

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