Senior Design Verification Engineer

Analog Devices

Systemverilog verification experience
Uvm environment development
Mixed signal design verification
Analog Devices is a global semiconductor leader bridging physical and digital worlds to enable breakthroughs at the Intelligent Edge

Job Summary

  • Analog Devices is a global semiconductor leader bridging physical and digital worlds to enable breakthroughs at the Intelligent Edge.
  • The role involves developing directed and constrained random test cases in SystemVerilog while managing metric-driven verification environments.
  • Candidates will work with analog and digital teams to enable top-level chip verification and support post-silicon activities.

Matching Summary

Analog Devices is a global semiconductor leader bridging physical and digital worlds to enable breakthroughs at the Intelligent Edge.

Skills & Requirements

Must-have

  • SystemVerilog verification experience
  • UVM environment development
  • Mixed signal design verification
  • Test plan generation and closure
  • Constrained random test case creation

Nice-to-have

  • Scripting language proficiency
  • Formal verification methodology
  • ARM/RISC-V subsystem experience
  • PMBUS and AVS interface knowledge
  • Cadence AMS simulation skills

Key Requirements

  • BSEE + 5 years or MSEE + 1 year experience
  • Strong SystemVerilog fluency in verification domain
  • Experience with SystemVerilog Assertions for dynamic and formal verification

Work Rights

US Citizens, US Permanent Residents, or protected individuals required; others need export licensing review

Tailored Resume

Cover Letter