Design, develop, validate, and/or debug software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients
Job Summary
Design, develop, validate, and/or debug software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.
Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM.
Matching Summary
Design, develop, validate, and/or debug software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.
Skills & Requirements
Must-have
SystemVerilog and UVM
coverage-driven verification
assertion-based verification
simulation and debug tools
Python or Perl scripting
Nice-to-have
collaborative cross-functional team
technical reviews and feedback
familiarity with industry-standard protocols
Key Requirements
9+ years of experience in ASIC or FPGA design verification
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field