Sr Principal Design Engineer- Memory Ip

Cadence

San Jose, CA, US
Base: $154,000 to $286,000; bonus/equity: eligible...
Bs degree with 8+ years experience
Ms degree with 6+ years experience
Proficiency in verilog/systemverilog
The role involves owning the IC micro-architecture, timing budget, and developing power analysis platforms for high-performance memory IP

Job Summary

  • The role involves owning the IC micro-architecture, timing budget, and developing power analysis platforms for high-performance memory IP.
  • Candidates must demonstrate strong communication skills and have at least five years of experience driving complex IC development projects.
  • The position offers a competitive salary range of $154,000 to $286,000 along with bonus, equity, and comprehensive benefits.

Matching Summary

The role involves owning the IC micro-architecture, timing budget, and developing power analysis platforms for high-performance memory IP.

Salary

Base: $154,000 to $286,000; Bonus/Equity: Eligible for incentive compensation including bonus and equity; Benefits: Paid vacation, holidays, 401(k) match, stock purchase plan, medical/dental/vision

Skills & Requirements

Must-have

  • BS degree with 8+ years experience
  • MS degree with 6+ years experience
  • Proficiency in Verilog/SystemVerilog
  • Experience driving complex IC projects
  • Strong verbal and written communication

Nice-to-have

  • Memory IP experience desired
  • Good knowledge of high-speed low power IC design
  • Ability to lead and contribute in cooperative team

Key Requirements

  • BS/MS in Electrical Engineering or related field
  • 8+ years applicable experience (BS) or 6+ (MS)
  • Proficiency in logic design, simulation, synthesis, STA, and testing

Work Rights

Not specified

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