Base + variable compensation ranges from $100k - $...
On-site
8+ years top-level soc physical design experience
Hierarchical floorplanning and fabric implementation
Power grid design and global clock distribution
Tenstorrent is seeking a Senior-level Physical Design Engineer to drive top-level implementation of complex AI and CPU System-on-Chip designs
Job Summary
Tenstorrent is seeking a Senior-level Physical Design Engineer to drive top-level implementation of complex AI and CPU System-on-Chip designs.
The role requires orchestrating cross-disciplinary collaboration while implementing sophisticated floorplans, power grids, and clock networks to ensure design closure.
Candidates will have the opportunity to learn cutting-edge techniques for AI accelerators, high-performance CPUs, and chiplet integration.
Matching Summary
Tenstorrent is seeking a Senior-level Physical Design Engineer to drive top-level implementation of complex AI and CPU System-on-Chip designs.
Salary
Base and variable compensation ranges from $100k - $500k; Experience and location impact actual offer; Competitive benefits package included
Skills & Requirements
Must-have
8+ years top-level SOC physical design experience
Hierarchical floorplanning and fabric implementation
Power grid design and global clock distribution
Bump planning and RDL implementation
Multi-voltage domain designs
Timing closure and EM/IR analysis
Physical verification at chip level
Nice-to-have
Cross-disciplinary collaboration skills
Passion for optimizing power performance area
Commitment to solving hard problems
Experience with chiplet integration
Next-generation packaging co-design knowledge
Key Requirements
8+ years of top-level SOC physical design experience
Complex multi-million gate design background
Eligibility for U.S. export license access
Mastery of timing closure and physical verification
Work Rights
Must be eligible for U.S. export license (not EAR Country Groups D:1, E1, or E2)