Senior Sta Engineer, Sub-chip

Invidia

Multiple Locations
Static timing analysis (sta)
Prime time and signoff methodologies
Timing closure and quality approval
NVIDIA is developing the industry's best high-speed communication devices with highest throughput and lowest latency

Job Summary

  • NVIDIA is developing the industry's best high-speed communication devices with highest throughput and lowest latency.
  • The role involves full timing closure and quality approval from pre-layout STA model through signoff while collaborating across multiple teams.
  • NVIDIA offers a meaningful, growing, and highly professional environment with forward-thinking people and opportunities to make significant technological impact.

Matching Summary

NVIDIA is developing the industry's best high-speed communication devices with highest throughput and lowest latency.

Skills & Requirements

Must-have

  • Static Timing Analysis (STA)
  • Prime Time and signoff methodologies
  • Timing closure and quality approval
  • Collaboration with physical design and RTL teams
  • AI tools for timing optimization

Nice-to-have

  • AI prompting experience
  • Linux environment experience
  • TCL, Python, shell scripting abilities
  • Data collection and analysis
  • Agentic Frameworks

Key Requirements

  • B.SC./ M.SC. in Electrical Engineering
  • At least 5+ years of hands-on STA experience
  • Experience in Prime Time and signoff methodologies
  • AI tools orientation or desire to learn

Work Rights

Not specified

Tailored Resume

Cover Letter