Lead Product Engineer - Design Verification (mm/vip)

Cadence

Ahmedabad, India
Memory protocols expertise
System verilog verification environments
Uvm methodology experience
The PE's main role is to help accelerate VIP Portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities

Job Summary

  • The PE's main role is to help accelerate VIP Portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities.
  • As a MM VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customers, providing training and developing collaterals.
  • The PE is expected to work independently and collaborate with other team members (R&D, Marketing, Customer Support, Field Teams) to ensure all dimensions of the product are aligned.

Matching Summary

The PE's main role is to help accelerate VIP Portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities.

Skills & Requirements

Must-have

  • Memory protocols expertise
  • System Verilog verification environments
  • UVM methodology experience
  • Customer design and verification flows
  • Pre-sales technical activities support

Nice-to-have

  • Creative problem-solving
  • Cross-functional collaboration
  • Raising the bar with integrity
  • Impactful technology work

Key Requirements

  • 4-8 years Design and Verification experience
  • BTech/BE/MTech/ME or equivalent
  • Familiarity with Memory protocols
  • DFI protocol knowledge is a plus

Work Rights

Not specified

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