Staff Engineer, Design Verification

Analog Devices Foundation

Milan, Italy
System verilog and uvm verification
Constrained random functional verification
Coverage and assertions
The Data Center and Energy group develops leading-edge Power Conversion solutions for the Data Center

Job Summary

  • The Data Center and Energy group develops leading-edge Power Conversion solutions for the Data Center.
  • Candidate will work with the latest verification methodologies on designs ranging from individual blocks to sub-system level verification.
  • We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Matching Summary

The Data Center and Energy group develops leading-edge Power Conversion solutions for the Data Center.

Skills & Requirements

Must-have

  • System Verilog and UVM verification
  • constrained random functional verification
  • coverage and assertions
  • gate-level simulations and debugging
  • leading-edge verification methodologies

Nice-to-have

  • technically mentoring and coaching junior engineers
  • proactive and result-oriented
  • strong interpersonal and teamwork skills

Key Requirements

  • 8+ years of experience in digital design
  • at least 3 years in digital verification
  • Bachelor's or Master’s degree in Electronics Engineering
  • Expertise in Verilog, System Verilog, UVM
  • object-oriented programming, scripting, and automation with Perl or Python

Work Rights

Not specified

Tailored Resume

Cover Letter