Senior Engineer - Soc Design Verification

NXP Semiconductors

Pune, India
Arm-based microcontrollers
Soc-level verification
Systemverilog, uvm
Develop and own SoC-level and/or IP-level verification suites with coverage goals

Job Summary

  • Develop and own SoC-level and/or IP-level verification suites with coverage goals.
  • Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.
  • Mentor junior team members while actively collaborating with design teams for issue resolution and sign-off.

Matching Summary

Develop and own SoC-level and/or IP-level verification suites with coverage goals.

Skills & Requirements

Must-have

  • ARM-based microcontrollers
  • SoC-level verification
  • SystemVerilog, UVM
  • constrained-random verification
  • RTL/netlist simulation
  • coverage goals

Nice-to-have

  • fast-paced environment
  • strong team player
  • excellent communication skills
  • low-power verification (UPF)
  • gate-level simulations
  • power-aware simulations
  • common Analog IPs

Key Requirements

  • 5-12 years in SoC/IP verification
  • Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering
  • C based DV experience
  • Verilog, SystemVerilog, UVM proficiency
  • Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium)
  • Verification of multiple interfaces (SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI) is desirable
  • Knowledge of Flash memory and security IPs is nice to have

Work Rights

Not specified

Tailored Resume

Cover Letter