Physical Security Engineer - Internship

Cadence

Cesson-Sévigné, France
**
Vhdl/verilog development
Fpga tools like vivado
Python, shell, makefiles scripting
** Cadence is seeking an intern for a Physical Security Engineer role, focused on the development and validation of security solutions for FPGA and ASIC platforms. The position requires collaboration with firmware and RTL teams, hands-on testing, and contributions to the design and specification of test platforms. **

Job Summary

  • The intern will contribute to the development and validation of Anti-Tamper and random generator solutions targeting FPGA and ASIC platforms.
  • Responsibilities include defining test platforms, executing test cases in simulation and on FPGA, and achieving functional coverage metrics.
  • The role requires collaboration with firmware and RTL teams to ensure proper implementation and observability of security IP solutions.

Matching Summary

Match Score: 75

** Cadence is seeking an intern for a Physical Security Engineer role, focused on the development and validation of security solutions for FPGA and ASIC platforms. The position requires collaboration with firmware and RTL teams, hands-on testing, and contributions to the design and specification of test platforms. **

Skills & Requirements

Must-have

  • VHDL/Verilog development
  • FPGA tools like Vivado
  • Python, Shell, Makefiles scripting

Nice-to-have

  • SystemC modeling experience
  • Git and CI/CD pipeline knowledge
  • Collaboration with firmware teams

Key Requirements

  • Master's Degree (M2) or final year Engineering student
  • Specialization in Electronics, Microelectronics, Embedded Systems, or Computer Engineering

Work Rights

Not specified

Tailored Resume

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