Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world
Job Summary
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
ASIC design engineer responsible for post-RTL design flow, including synthesis, timing closure, DFT generation, and ECOs.
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.
Matching Summary
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
Skills & Requirements
Must-have
post-RTL design flow
synthesis and timing closure
DFT generation and verification
physical design for 28nm and beyond
logic or physical synthesis
static timing analysis
Perl and Tcl scripting skill
Nice-to-have
improve design methodology and flow
low power design
circuit level or custom design
floorplanning, clock-tree synthesis
signal integrity and physical verification
Key Requirements
Master’s degree and/or PhD in EE, CS or related fields
6+ years of experience
good post-RTL experience
custom placement and routing for mixed-signal designs