2+ years layout experience for highspeed analog ic
Finfet technology expertise
The role involves designing and developing layouts for sophisticated advanced node CMOS products including PLL, DLL, ADC, and CDRs
Job Summary
The role involves designing and developing layouts for sophisticated advanced node CMOS products including PLL, DLL, ADC, and CDRs.
Candidates will manage manufacturing processes to ensure technology yield and product performance while minimizing parasitic effects and skew.
The position requires collaboration with design engineers across multiple time zones to create high-quality layouts adhering to strict DRC and LVS rules.
Matching Summary
Match Score: 85
The role involves designing and developing layouts for sophisticated advanced node CMOS products including PLL, DLL, ADC, and CDRs.
Skills & Requirements
Must-have
Bachelor's degree in electrical engineering
2+ years layout experience for highspeed analog IC
FinFET technology expertise
Layout extraction tools proficiency
EMIR and antenna DRC rules awareness
Nice-to-have
SKILL and TCL scripting capabilities
Team-oriented work style across time zones
Experience with advanced CMOS nodes
Key Requirements
At least a bachelor's degree in electrical engineering
Minimum 2 years of experience in highspeed analog IC layout development
Proficiency with layout extraction tools for parasitic analysis