Lead and drive functional verification for complex ASIC/SoC designs, ensuring standards compliance, performance, interoperability, and robustness of Ethernet products
Job Summary
Lead and drive functional verification for complex ASIC/SoC designs, ensuring standards compliance, performance, interoperability, and robustness of Ethernet products.
Define and own verification strategy and methodology at IP, subsystem, and SoC levels, architecting scalable verification environments and reusable VIPs.
Collaborate closely with architecture, RTL, DFT, physical design, firmware, and software teams, providing early verification input and supporting post-silicon validation.
Matching Summary
Lead and drive functional verification for complex ASIC/SoC designs, ensuring standards compliance, performance, interoperability, and robustness of Ethernet products.
Skills & Requirements
Must-have
SystemVerilog, UVM, SVA expertise
Ethernet architecture and protocols
Verification strategy and methodology
Coverage-driven verification
RTL, DFT, physical design collaboration
Nice-to-have
Mentoring and technical guidance
Continuous improvement in verification flows
Emulation and FPGA prototyping support
Key Requirements
10+ years ASIC/SoC design verification experience
Bachelor’s or Master’s degree in Electrical/Electronics Engineering