Performance Architect

Cadence

Austin, TX, US
10+ years soc or system architecture experience
Deep expertise in armv8/armv9 cpu architectures
Performance modeling using transaction-level or analytical methods
This senior role requires defining and optimizing performance across CPUs, interconnects, and memory subsystems for ARM-based SoCs

Job Summary

  • This senior role requires defining and optimizing performance across CPUs, interconnects, and memory subsystems for ARM-based SoCs.
  • Candidates will drive architectural trade-offs involving latency, bandwidth, power, and area while evaluating chiplet partitioning impacts.
  • The position involves building system-level performance models and influencing decisions through data-driven analysis with cross-functional teams.

Matching Summary

This senior role requires defining and optimizing performance across CPUs, interconnects, and memory subsystems for ARM-based SoCs.

Skills & Requirements

Must-have

  • 10+ years SoC or system architecture experience
  • Deep expertise in ARMv8/ARMv9 CPU architectures
  • Performance modeling using transaction-level or analytical methods
  • Optimization of NoC fabric architectures and QoS
  • Experience with chiplet partitioning and die-to-die interconnects

Nice-to-have

  • Mentorship and technical leadership capabilities
  • Experience with heterogeneous workloads like NPU/AI
  • Strong cross-functional communication skills
  • Knowledge of UCIe-class link protocols
  • Ability to correlate models with RTL or silicon data

Key Requirements

  • 10+ years of experience in SoC or system architecture
  • Proven background working on ARM-based systems
  • Staff-level expectations for technical depth

Work Rights

Not specified

Tailored Resume

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