Asic/soc verification from specification to tape out
Low power verification with upf/cpf flow
This role involves architecting, enhancing, and maintaining advanced UVM-based and C-based verification environments for next-generation automotive products
Job Summary
This role involves architecting, enhancing, and maintaining advanced UVM-based and C-based verification environments for next-generation automotive products.
You will define robust verification strategies, craft comprehensive test plans, and drive metric-driven verification to full closure.
The position requires close collaboration with design, architecture, validation, and firmware teams to ensure quality and timely delivery of automotive solutions.
Matching Summary
This role involves architecting, enhancing, and maintaining advanced UVM-based and C-based verification environments for next-generation automotive products.
Skills & Requirements
Must-have
UVM and System Verilog verification
ASIC/SoC verification from specification to tape out
Low power verification with UPF/CPF flow
Directed and constrained random stimulus generation
C/C++ and scripting with Perl and Python
Verification metric closure and coverage analysis
Regression setup and debug of RTL and gate level netlist
Nice-to-have
Collaboration with cross-functional teams
Experience with GIT, Jira, Confluence tools
Development of UVM components like agents and scoreboards
Architecting verification strategies for IP and SoC
Functional coverage and assertion development
Key Requirements
B.S./M.S. in Electrical or Computer Engineering
8+ years ASIC/SoC verification experience
Proven expertise in UVM and System Verilog
Experience with low power verification and UPF/CPF