Senior / Lead Ddr Engineer

Hireroo

Barcelona, Spain
On-site
Ddr or hbm memory systems
Memory controller design and integration
Rtl design using verilog or vhdl
Our client is expanding their hardware engineering team and is looking for experienced engineers with a strong background in memory subsystem design

Job Summary

  • Our client is expanding their hardware engineering team and is looking for experienced engineers with a strong background in memory subsystem design.
  • The role offers flexible working hours, a hybrid model with one day remote per week, relocation support including flight, visa, accommodation, and family assistance.
  • The position provides career growth opportunities in a collaborative and dynamic environment, with benefits such as private medical insurance, virtual shares, and Spanish language classes.

Matching Summary

Our client is expanding their hardware engineering team and is looking for experienced engineers with a strong background in memory subsystem design.

Skills & Requirements

Must-have

  • DDR or HBM memory systems
  • Memory controller design and integration
  • RTL design using Verilog or VHDL
  • AXI or AMBA protocol experience
  • Timing constraints and timing analysis
  • Block level testing methodologies
  • Hybrid work model in Barcelona

Nice-to-have

  • Technical project leadership
  • Cross functional team coordination
  • Mentoring and communication skills
  • Python, Perl, Bash or TCL scripting
  • Version control systems like git or svn
  • Coherency concepts and protocols
  • Memory map definition experience
  • Master or PhD degree

Key Requirements

  • 8+ years industrial experience
  • Proven memory subsystem design ownership
  • Experience leading technical projects or small teams
  • Ability to define architecture and drive decisions

Work Rights

Not specified

Tailored Resume

Cover Letter