Application Engineer I: Digital Verification & Simulation

Cadence Design Systems Inc.

Belo Horizonte, Brazil
Not specified; not specified; competitive benefits
Bachelor's degree in engineering
Solid foundation in digital logic
Knowledge of systemverilog or verilog
The role involves assisting customers in improving verification productivity and simulation performance using Cadence digital verification tools

Job Summary

  • The role involves assisting customers in improving verification productivity and simulation performance using Cadence digital verification tools.
  • Candidates will collaborate with senior engineers and R&D teams to reproduce issues, analyze root causes, and validate solutions.
  • Cadence is a Fortune 100 Best Companies to Work For globally and has been nominated as a Great Place to Work.

Matching Summary

The role involves assisting customers in improving verification productivity and simulation performance using Cadence digital verification tools.

Salary

Not specified; Not specified; Competitive benefits

Skills & Requirements

Must-have

  • Bachelor's degree in Engineering
  • Solid foundation in digital logic
  • Knowledge of SystemVerilog or Verilog
  • Familiarity with simulation-based verification
  • Basic scripting experience with TCL Python

Nice-to-have

  • Exposure to functional verification flows
  • Understanding of SystemVerilog testbench concepts
  • Familiarity with coverage analysis concepts
  • Prior exposure to Cadence Xcelium tools
  • Experience with Linux development environments

Key Requirements

  • Complete Bachelor's degree in Electrical or Computer Engineering
  • Strong analytical and debugging skills required

Work Rights

Not specified

Tailored Resume

Cover Letter