Design Verification Engineer Iv

Arrow Electronics Inc

San Jose, California, US
$112,200.00 - $176,000.00 py
On-site
Architecting verification environment
Constraint random stimulus generation
Soc asic platform test fw
Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development

Job Summary

  • Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development.
  • Develop complex self checking test benches with constraint random stimulus generation.
  • Develop and debug SoC ASIC platform test FW and specific tests in C/C++.

Matching Summary

Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development.

Salary

$112,200.00 - $176,000.00

Skills & Requirements

Must-have

  • architecting Verification Environment
  • constraint random stimulus generation
  • SoC ASIC platform test FW
  • formal verification flow
  • automate the verification process

Nice-to-have

  • partner in methodology development
  • acts as a resource for colleagues

Key Requirements

  • 8 years of related experience with a 4 year degree
  • 6 years and an advanced degree
  • equivalent experience

Work Rights

Not specified

Tailored Resume

Cover Letter