The candidate will be part of a team implementing ASIC designs for Integrated/Discrete Graphics and AI SoCs on leading edge process technology and EDA tools
Job Summary
The candidate will be part of a team implementing ASIC designs for Integrated/Discrete Graphics and AI SoCs on leading edge process technology and EDA tools.
The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects.
Good leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team.
Matching Summary
The candidate will be part of a team implementing ASIC designs for Integrated/Discrete Graphics and AI SoCs on leading edge process technology and EDA tools.
Skills & Requirements
Must-have
SoC level physical design and optimization
Floor-planning, Clocking, Synthesis
Static Timing Analysis, Formal Verification
Layout Verification
Unix/Linux, Perl and TCL scripting
Nice-to-have
SoC integration methodologies
Fullchip design planning
Clock construction methodology
Timing budgeting and repeater optimization
Key Requirements
Bachelor’s in Electrical/Computer Engineering with 9+ years relevant work experience
Master's in Electrical/Computer Engineering with 6+ years relevant work experience
Experience in Logic Design, VLSI/ASIC Design, Computer Architecture
Current Industry Experience in ASIC style design flows