Silicon Design Flow Methodology And Automation - Lec.
Altera
Penang, Malaysia
Logic equivalence check lec flows
Cadence conformal or synopsys formality
Atpg model generation and gln
This role focuses on defining, developing, and maintaining scalable automation and methodologies for silicon design verification and test enablement
Job Summary
This role focuses on defining, developing, and maintaining scalable automation and methodologies for silicon design verification and test enablement.
The engineer will own end-to-end Logic Equivalence Check flows using industry-standard tools like Cadence Conformal and Synopsys Formality.
Collaboration with DFT, ATPG, RTL, synthesis, and physical design teams is essential to deliver robust automated solutions across multiple technology nodes.
Matching Summary
This role focuses on defining, developing, and maintaining scalable automation and methodologies for silicon design verification and test enablement.
Skills & Requirements
Must-have
Logic Equivalence Check LEC flows
Cadence Conformal or Synopsys Formality
ATPG model generation and GLN
ECO verification flows
Tcl Python Perl shell scripting
Nice-to-have
AI ML techniques for flow efficiency
Experience with multiple EDA domains
Version control systems Git Perforce
Advanced technology node experience
Cross-domain design automation efforts
Key Requirements
Bachelor's or Master's degree in related field
5+ years of experience in silicon design automation
Strong hands-on experience with LEC and ECO verification