Validates and researches the Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features like SignalTap using Quartus Design Software and Altera FPGA Hardware
Job Summary
Validates and researches the Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features like SignalTap using Quartus Design Software and Altera FPGA Hardware.
Creates Altera device-specific testcases with Verilog/VHDL and Altera IPs and verifies them for timing & functionality using industry-standard simulation and formal verification tools.
Collaborates with cross-functional teams to develop and improve Synthesis & Compiler test coverage and helps resolve customer issues as they occur.
Matching Summary
Validates and researches the Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features like SignalTap using Quartus Design Software and Altera FPGA Hardware.
Skills & Requirements
Must-have
FPGA/ASIC RTL Design
RTL design and verification
VHDL, Verilog or SystemVerilog
Altera Quartus, Xilinx Vivado
FPGA Partial Reconfiguration (PR) flow
HW debugging skills
Simulation/Verification of digital designs
Timing Analysis (STA)
Nice-to-have
Shell, Perl, TCL or Python Scripting
AHB, AXI, PCIe, Ethernet, Avalon bus protocols
High-Speed interfaces
Key Requirements
Min. 5+ years of relevant experience
Master's/Bachelor's Degree in Electronics/VLSI/Digital Design