Cadence Silicon Solutions Group (SSG) develops leading-edge Intellectual Property (IP) for a variety of High-Tech Markets, enabling customers to tackle IP-to-SoC development in a system context
Job Summary
Cadence Silicon Solutions Group (SSG) develops leading-edge Intellectual Property (IP) for a variety of High-Tech Markets, enabling customers to tackle IP-to-SoC development in a system context.
The Principal Verification Engineer will be responsible for the architecture of verification environments, development of UVM-SV Scoreboards, functional coverage, SystemVerilog Assertions, and management of verification plans and automated regression environments.
Cadence is committed to equal employment opportunity and employment equity, striving to attract a qualified and diverse candidate pool and encouraging diversity and inclusion in the workplace.
Matching Summary
Cadence Silicon Solutions Group (SSG) develops leading-edge Intellectual Property (IP) for a variety of High-Tech Markets, enabling customers to tackle IP-to-SoC development in a system context.
Skills & Requirements
Must-have
Architecture of Verification Environments
UVM-SV Scoreboards development
Functional Coverage development
SystemVerilog Assertions development
Verification Plans management
Automated Regression Environments creation
Nice-to-have
Self-motivated with excellent planning
Interpersonal and communication skills
Experience of Front-end design tools
Experience of Quality processes
AXI and/or CHI experience
Key Requirements
10-15 years' experience in microelectronics/EDA
Verilog RTL Design experience essential
Metric Driven Verification (MDV) essential
Excellent oral and written English essential
Degree in Electrical/Electronic Engineering or related discipline