Senior Silicon Design Engineer

Intel Retiree Medical Plan Trust

Penang, Malaysia
10+ years asic/soc implementation experience
Rtl to gds physical design flow expertise
Synthesis place and route clock tree synthesis
The role involves performing physical design implementation of complex custom IP and SoC designs from RTL to GDS for manufacturing readiness

Job Summary

  • The role involves performing physical design implementation of complex custom IP and SoC designs from RTL to GDS for manufacturing readiness.
  • Candidates must possess a strong background in scripting languages such as PERL, TCL, and Python to optimize design methodologies.
  • This position requires on-site presence at the Penang, Malaysia location within Intel's Central Engineering Group.

Matching Summary

The role involves performing physical design implementation of complex custom IP and SoC designs from RTL to GDS for manufacturing readiness.

Skills & Requirements

Must-have

  • 10+ years ASIC/SOC implementation experience
  • RTL to GDS physical design flow expertise
  • Synthesis place and route clock tree synthesis
  • Static timing analysis and power distribution
  • Formal equivalence verification and reliability
  • PERL TCL Python scripting proficiency

Nice-to-have

  • Experience with PCIE USB DDR protocols
  • Low power UPF implementation knowledge
  • Formal verification techniques background
  • CPU GPU Media block design experience
  • Memory controller design expertise

Key Requirements

  • Btech/Mtech degree required
  • 10+ years of complex ASIC/SOC implementation experience
  • System Verilog SOC development environment knowledge
  • Hardware validation techniques understanding
  • On-site work requirement in Malaysia

Work Rights

Not specified

Tailored Resume

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