Job Summary

• Altera is looking for a talented and driven Verification Engineer to design, develop, validate, and debug software abstractions and frameworks for acceleration with FPGAs.
• Key responsibilities include collaborating with architects, defining verification strategies, developing reusable verification environments using SystemVerilog and UVM, and executing simulation regressions.
• The role requires a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, with 9+ years of experience in ASIC or FPGA design verification.

Matching Summary

Skills & Requirements

Key Requirements

• 9+ years of experience
• Bachelor's or Master's degree
• Expertise in Verilog or VHDL
• Expertise in SystemVerilog
• Strong UVM experience
• Proficiency in CDV and ABV
• Strong scripting skills

Work Rights