Asic Engineer - Sdc

Cisco UK

San Jose, CA, USA
Base: $165,000.00 - $241,400.00; bonus/equity: ann...
Onsite
Full-chip timing constraints (sdc)
Static timing analysis (sta)
Timing convergence
Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks

Job Summary

  • Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.
  • Own and develop full-chip timing constraints (SDC) across functional and test modes for complex networking SoCs.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.

Salary

Base: $165,000.00 - $241,400.00; Bonus/Equity: Annual bonuses, restricted stock units; Benefits: Medical, dental, vision, 401(k) with match, paid leave

Skills & Requirements

Must-have

  • full-chip timing constraints (SDC)
  • Static Timing Analysis (STA)
  • timing convergence
  • clocking architectures
  • third-party IP integration

Nice-to-have

  • constraint analysis tools
  • CDC analysis tools
  • Python, Perl, TCL scripting

Key Requirements

  • 7+ years ASIC experience (Bachelor's)
  • 4+ years ASIC experience (Master's)
  • 1+ years ASIC experience (PhD)
  • Experience developing block-level and full-chip SDC constraints
  • Expertise in Static Timing Analysis (STA)
  • Experience writing timing constraints for complex networking SoCs and ARM CPU subsystems
  • Experience integrating third-party IP timing constraints

Work Rights

Not specified

Tailored Resume

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