Talentlab Inc is seeking a Senior Staff ASIC Design Engineer for a global semiconductor leader in Toronto, Ontario. The role involves developing advanced AI/ML hardware IP and requires extensive experience in ASIC design, RTL development, and SoC integration
Job Summary
Define and implement micro-architecture based on high-level AI/ML design requirements.
Own RTL development (Verilog/SystemVerilog), optimizing for performance, area, and power.
Partner closely with verification teams on test plans, debug, and functional coverage.
Matching Summary
Match Score: 85
Talentlab Inc is seeking a Senior Staff ASIC Design Engineer for a global semiconductor leader in Toronto, Ontario. The role involves developing advanced AI/ML hardware IP and requires extensive experience in ASIC design, RTL development, and SoC integration.
Skills & Requirements
Must-have
RTL development (Verilog/SystemVerilog)
AI/ML-specific hardware acceleration
Clock/reset architecture, FIFOs, memory control
Power-aware design and low-power optimization
Bus protocols (AHB, AXI)
Simulation (VCS, Verdi, Questa, Xcelium)
CDC/lint/formal tools (Spyglass, 0-in, Formality)
Synthesis/timing (DCG/NXT, Primetime)
Nice-to-have
Cross-functional leadership
Best practices in design and integration
Python, Perl, TCL, C scripting
Key Requirements
6+ years ASIC design experience
Master’s + 5 years experience
PhD + 4 years experience
Bachelor’s, Master’s, or PhD in Electrical Engineering
Work Rights
Must be legally authorized to work on-site in Canada