Senior Digital Verification Engineer

NXP USA INC.

Systemverilog and uvm proficiency
Asic verification experience
Tape-out cycle participation
The role involves leading the implementation and execution of verification for IP blocks and sub-systems within a collaborative ASIC engineering team

Job Summary

  • The role involves leading the implementation and execution of verification for IP blocks and sub-systems within a collaborative ASIC engineering team.
  • Candidates will develop advanced UVM components including agents, monitors, and scoreboards to validate functional correctness and corner cases.
  • The position requires contributing to verification closure by analyzing coverage results and collaborating with design engineers to resolve RTL issues.

Matching Summary

The role involves leading the implementation and execution of verification for IP blocks and sub-systems within a collaborative ASIC engineering team.

Skills & Requirements

Must-have

  • SystemVerilog and UVM proficiency
  • ASIC verification experience
  • Tape-out cycle participation
  • Directed and constrained-random testing
  • Functional coverage analysis

Nice-to-have

  • Low-power verification concepts
  • HW-FW co-verification skills
  • C/C++ programming for tests
  • Python or Perl scripting
  • Strong problem-solving abilities

Key Requirements

  • 6 to 10 years industry experience
  • At least one tape-out cycle
  • Proficiency in SystemVerilog and UVM

Work Rights

Not specified

Tailored Resume

Cover Letter