Lead Verification Engineer

BETA CAE Systems International AG

Hsinchu, Taiwan
On-site
Pre-silicon verification
Formal verification
Uvm verification
BETA CAE Systems International AG is seeking a Lead Verification Engineer in Hsinchu, Taiwan, with a focus on pre-silicon verification methodologies and a passion for leveraging AI in semiconductor design. The ideal candidate should have substantial experience in functional verification and a strong background in programming and EDA tools

Job Summary

  • Operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies.
  • Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
  • Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.

Matching Summary

Match Score: 85

BETA CAE Systems International AG is seeking a Lead Verification Engineer in Hsinchu, Taiwan, with a focus on pre-silicon verification methodologies and a passion for leveraging AI in semiconductor design. The ideal candidate should have substantial experience in functional verification and a strong background in programming and EDA tools.

Skills & Requirements

Must-have

  • Pre-Silicon Verification
  • Formal Verification
  • UVM Verification
  • AI Tools for Verification
  • System Verilog
  • Python

Nice-to-have

  • LLMs and ML technologies
  • Customer engagement
  • Knowledge growth

Key Requirements

  • Bachelor's degree with 4 years of experience or Master's degree with 2 years of experience
  • Experience in Formal, SV/UVM and/or OVM
  • Debugging pre-silicon verification failures
  • Experience with EDA tools (Jasper, Xcelium, IMC)
  • Verilog, System Verilog and Python programming skills

Work Rights

Not specified

Tailored Resume

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