NXP Semiconductors is seeking a Lead DFT Engineer in Pune, India, responsible for designing and implementing DFT architectures for complex SoCs. The ideal candidate will have extensive experience in DFT methodologies and a strong background in collaboration across various engineering teams
Job Summary
Responsible for designing, implementing, and verifying DFT architectures for complex SoCs.
Collaborate with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.
Work with ATE teams for test program development and silicon bring-up.
Matching Summary
Match Score: 85
NXP Semiconductors is seeking a Lead DFT Engineer in Pune, India, responsible for designing and implementing DFT architectures for complex SoCs. The ideal candidate will have extensive experience in DFT methodologies and a strong background in collaboration across various engineering teams.
Skills & Requirements
Must-have
DFT methodologies: Scan, MBIST, LBIST, JTAG
industry standard ATPG tools
UPF/CPF-based low-power DFT
fault models (stuck-at, transition, path delay)
physical design constraints for DFT
silicon debug and ATE bring-up
Nice-to-have
SoC level DFT experience
high-speed interfaces and DFT
mixed-signal blocks DFT
strong problem-solving skills
communication skills
Key Requirements
Bachelor’s or Master’s in Electrical/Electronics Engineering