Memory Design Automation – Memory Modeling, Senior/Staff Engineer

PERSOL SINGAPORE PTE. LTD.

Singapore, Singapore
Not specified
Memory modeling and compiler automation
Perl or python scripting skills
Verilog syntax understanding
PERSOL Singapore is seeking a Senior/Staff Engineer for Memory Design Automation, focusing on developing automation code for memory compilers in the ASIC design flow. The ideal candidate should possess a strong background in electrical engineering or a related field, alongside experience in scripting and EDA tools

Job Summary

  • The role involves developing and integrating automation code into existing memory compilers to generate models for the ASIC design flow.
  • Candidates must possess a strong understanding of Verilog syntax, Liberty timing syntax, UPF, and SystemVerilog to ensure model correctness.
  • The position requires executing EDA tools from vendors like Synopsys and Mentor while collaborating with memory design and DFT teams.

Matching Summary

Match Score: 85

PERSOL Singapore is seeking a Senior/Staff Engineer for Memory Design Automation, focusing on developing automation code for memory compilers in the ASIC design flow. The ideal candidate should possess a strong background in electrical engineering or a related field, alongside experience in scripting and EDA tools.

Skills & Requirements

Must-have

  • Memory modeling and compiler automation
  • Perl or Python scripting skills
  • Verilog syntax understanding
  • Liberty timing syntax knowledge
  • UPF and SystemVerilog expertise
  • VCS or NC simulation tool experience

Nice-to-have

  • DFT tool experience (Logicvision, Tessent)
  • Synthesis tool familiarity (Design Compiler, Genus)
  • STA tool knowledge (PrimeTime)
  • Team player with independent learning ability
  • Meticulous attention to detail

Key Requirements

  • Bachelor's degree in Electrical Engineering
  • Relevant semiconductor industry experience
  • Linux system proficiency

Work Rights

Not specified

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